FIG. 1 illustrates an example memory cell structure according to the state of the art. This memory cell comprises a bistable circuit 1 based on transistors made using the CMOS technology. This bistable circuit is typically composed of two cross coupled inverters Inv1 and Inv2, each inverter then forming a storage node and having complementary read/write terminals Q and Qb. Each storage node Inv1 and Inv2 is composed of an NMOS transistor N1 and N2 respectively, and a PMOS transistor P1 and P2 respectively.
The PMOS transistor of each storage node is programmable, such that the threshold voltage of one PMOS can be offset from the threshold voltage of the other PMOS, and consequently the threshold voltage of one inverter can be offset from the threshold voltage of the other. The two inverters having different threshold voltages, when the cell is loaded, one of the two inverters is thus designed to switch more quickly than the other so that, depending on the state of programming, the required logical information 1 or 0 can be picked up on terminal Q, and the complementary logical state is then reached on terminal Qb.
For example, consider the case in which the PMOS transistor P1 of inverter Inv1 is programmed such that its threshold voltage Vth1 is greater than the threshold voltage Vth2 of the PMOS transistor P2 of the inverter Inv2 (in this case we are referring to the absolute value, as is the case for the entire description given below). In this configuration, a reset phase is carried out when the voltage is applied, during which the two PMOS transistors P1 and P2 are made conducting while the two NMOS transistors N1 and N2 are blocked. However, considering that the threshold voltage Vth1 is chosen to be greater than the threshold voltage Vth2, the transistor P2 is faster and will change over before the other PMOS transistor such that terminal Q will change to “0” when the power supply Vdd is stabilized, while at the same time the complementary logical state “1” is reached on terminal Qb.
Similarly, if we choose Vth1<Vth2 after the pre-load phase as the power supply Vdd is increasing, the logical states “1” and “0” are reached on terminals Q and Qb respectively.
In this configuration, the memory cell is necessarily initialized during the power supply increase phase. Such an operation implies that some specific constraints have to be taken into account during the power supply increase phase, particularly concerning the power supply voltage set-up time. If the increase in the power supply voltage is too fast, the behaviour of the cell may be severely disturbed, so that the cell can even be initialized in the inverse manner to what is normally expected. Therefore, one operating mode of such memory cell implies a fairly slow increase in the power supply voltage, of the order of a few milliseconds.
Furthermore, another constraint to be taken into account relates to the size of transistors involved in these cells. More precisely, fairly large transistors have to be provided to overcome undesirable effects related to mismatches. Repeatability problems in the transistor manufacturing process can mean that MOS transistors designed to be strictly identical, actually have different characteristics, for example in terms of their gate length. By choosing large transistors, the variation of the gate length as a function of the total length then becomes too small to influence operation.
But although this choice makes the assembly more robust, it is made at the detriment of other necessities and particularly security, because due to their size, these memory cells are then easily identifiable within a circuit. They can then be unsuitable for some security applications.